As operating frequencies increase to hundreds of megahertz (MHz) for multimedia processors and application specific integrated circuits (ASICs), and increase to around a gigahertz (GHz) for the next generation of central processing units (CPUs), global electrical signals, for example, reset, stall, clock, and control, have less time to traverse an integrated circuit (IC) on a microchip (chip) due to reduced cycle time. The problem is compounded even further as IC chips get larger and larger. Therefore, global signals often exhibit larger than desirable propagation delays, and the circuits which provide these signals need to be optimized so that signals may meet timing specifications.
Generally, the propagation delay associated with a signal, or the time necessary for the signal to propagate from one point to another on a chip, is caused by resistances and/or capacitances imposed upon the signal path, and is sometimes referred to as “RC delay.” These resistances and capacitances also degrade the signal (decrease its rising/falling slope) as the signal propagates along a connection, which is another undesirable deleterious effect.
Many diverse approaches to this problem have been developed by researchers and published in the past few years. Consider the following, as examples: (1) N. Menezes, R. Baldick, and L. T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate,” Department of Electrical and Computer engineering, University of Texas at Austin, ICCAD, November 1995; (2) J. Lillis, C. K. Cheng, and T. T. Lin, “Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model,” University of California, San Diego, Calif., ICCAD, Nov. 1996; (3) J. Cong, and C. K. Koh, “Simultaneous Driver and Wire Sizing for Performance and Power Optimization,” University of California, Los Angeles, Calif., IEEE, Transactions on Very Large Scale Integration Systems, Vol. 2, No. 4, December 1994; and (4) L. P. Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” IBM, NY, IEEE International Symposium on Circuits and Systems, 1990.
One effective technique in reducing the delay of a signal involves inserting a “repeater” (also referred to in the art as a “driver” or “buffer”) along the signal path. A repeater is generally a circuit, for example, an inverter or set of cascaded inverters, that reduces the RC delay and slope degradation of the propagated signal. Historically, determining where to insert repeaters has been accomplished by creating and analyzing models of IC circuits. A mathematical algorithm known as “Elmore” has been used in the past to compute RC delays before and after introduction of repeaters in a circuit. The Elmore algorithm is described in L. P. Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” IBM, NY, IEEE International Symposium on Circuits and Systems, 1990. However, this process is time consuming and has traditionally been performed by having an engineer or designer review circuit models and determine where to insert repeaters.
Software tools for modeling and simulating circuits are well known in the art. Well known delay simulators (or calculators) include, for example, SPICE and OPTspice (available from Hewlett-Packard Company, U.S.A.). Although the foregoing software programs can be used for modeling and simulations, they do not automatically determine where and to what extent repeaters should be placed within a circuit, nor do they allow a user to specify interconnect specifications in conjunction with repeater insertion and to see the effects on propagation delay caused by such insertion.
Thus, a heretofore unaddressed need exists in the industry for a way to automatically and efficiently determine the most efficient positioning of repeaters when designing an IC in order to reduce signal propagation delays in the IC.